AT91RM9200_14 Datasheet, PDF (263/701 Pages) ATMEL Corporation – 200 MIPS at 180 MHz, Memory Management Unit

AT91RM9200
23.3 Block Diagram
Figure 23-1. Power Management Controller Block Diagram
Power Management Controller
Clock Generator
Processor
Clock
Controller
Idle Mode
XIN32
XOUT32
XIN
XOUT
Slow Clock
Oscillator
Main
Oscillator
Slow
Clock
SLCK
Main
Clock
SLCK
Main Clock
PLLA Clock
PLLB Clock
Master Clock Controller
Prescaler
/2,/4,...,/64
Divider
/1,/2,/3,/4
ARM9-systems
only
PLLRCA
PLLRCB
PLL and
Divider A
PLL and
Divider B
PLLA
Clock
PLLB
Clock
Peripherals
30
Clock Controller
ON/OFF
PLLB
Clock
USB Clock
Controller
ON/OFF
Programmable Clock Controller
SLCK
Main Clock
Prescaler
4
PLLA Clock
/2,/4,...,/64
PLLB Clock
Processor
Clock
Processor
Clock
IRQ or FIQ
PMCIRQ
MCK
(Continuous)
MCK
(Individually
Switchable)
UDPCK
Suspend
UHPCK
Programmable
Clocks
User Interface
Slow
Clock
SLCK
SLCK
APB
ARM7
Processor
ARM920T
Processor
AIC
Memory Controller
Embedded
Peripherals
UDP
UHP
PIO
ST
RTC
PCK0-PCK3
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