AT83C51SND1C_03 Datasheet, PDF (37/210 Pages) ATMEL Corporation – Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface

AT8xC51SND1C
Table 49. Priority Levels
IPHxx
IPLxx
Priority Level
0
0
0 Lowest
0
1
1
1
0
2
1
1
3 Highest
A low-priority interrupt is always interrupted by a higher priority interrupt but not by
another interrupt of lower or equal priority. Higher priority interrupts are serviced before
lower priority interrupts. The response to simultaneous occurrence of equal priority inter-
rupts is determined by an internal hardware polling sequence detailed in Table 50.
Thus, within each priority level there is a second priority structure determined by the
polling sequence. The interrupt control system is shown in Figure 21.
Table 50. Priority within Same Level
Interrupt Name
INT0
Timer 0
INT1
Timer 1
Serial Port
MP3 Decoder
Audio Interface
MMC Interface
Two Wire Controller
SPI Controller
A to D Converter
Keyboard
Reserved
USB
Reserved
Priority Number
1 (Highest Priority)
2
3
4
5
6
7
8
9
10
11
12
13
14
15 (Lowest Priority)
Interrupt Address
Vectors
C:0003h
C:000Bh
C:0013h
C:001Bh
C:0023h
C:002Bh
C:0033h
C:003Bh
C:0043h
C:004Bh
C:0053h
C:005Bh
C:0063h
C:006Bh
C:0073h
Interrupt Request Flag
Cleared by Hardware
(H) or by Software (S)
H if edge, S if level
H
H if edge, S if level
H
S
S
S
S
S
S
S
S
-
S
-
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4109E–8051–06/03