ATXMEGA128A4 Datasheet, PDF (36/69 Pages) ATMEL Corporation – 8/16-bit XMEGA A4 Microcontroller

XMEGA A4
21. USART
21.1 Features
21.2 Overview
• Five Identical USART peripherals
• Full Duplex Operation (Independent Serial Receive and Transmit Registers)
• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High-resolution Arithmetic Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data OverRun Detection
• Framing Error Detection
• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication Mode
• Master SPI mode for SPI communication
• IrDA support through the IRCOM module
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication module. The USART supports full duplex communication,
and both asynchronous and clocked synchronous operation. The USART can also be set in
Master SPI mode to be used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide
range of standards. The USART is buffered in both direction, enabling continued data transmis-
sion without any delay between frames. There are separate interrupt vectors for receive and
transmit complete, enabling fully interrupt driven communication. Frame error and buffer over-
flow are detected in hardware and indicated with separate status flags. Even or odd parity
generation and parity check can also be enabled.
One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modula-
tion and demodulation for baud rates up to 115.2 kbps.
PORTC and PORTD each has two USARTs. PORTE has one USART. Notation of these periph-
erals are USARTC0, USARTC1, USARTD0, USARTD1 and USARTE0, respectively.
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