ATXMEGA128A4 Datasheet, PDF (12/69 Pages) ATMEL Corporation – 8/16-bit XMEGA A4 Microcontroller

XMEGA A4
7.7 Flash and EEPROM Page Size
Devices
ATxmega16A4
ATxmega32A4
ATxmega64A4
ATxmega128A4
The Flash Program Memory and EEPROM data memory is organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 12 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at the time, while reading the Flash is done one byte at
the time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant
bits in the address (FPAGE) gives the page number and the least significant address bits
(FWORD) gives the word in the page.
Table 7-2. Number of words and Pages in the Flash.
Flash
Page Size
FWORD
FPAGE
Application
Size (Bytes)
(words)
Size
No of Pages
16K + 4K
128
Z[6:0]
Z[13:7]
16K
64
32K + 4K
128
Z[6:0]
Z[14:7]
32K
128
64K + 4K
128
Z[6:0]
Z[15:7]
64K
128
128K + 4K
256
Z[7:0]
Z[16:8]
128K
256
Size
4K
4K
4K
4K
Boot
No of Pages
16
16
16
16
Devices
ATxmega16A4
ATxmega32A4
ATxmega64A4
ATxmega128A4
Table 7-3 on page 12 shows EEPROM memory organization for the XMEGA A4 devices.
EEPROM write and erase operations can be performed one page or one byte at the time, while
reading the EEPROM is done one byte at the time. For EEPROM access the NVM Address
Register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE)
gives the page number and the least significant address bits (E2BYTE) gives the byte in the
page.
Table 7-3.
EEPROM
Size (Bytes)
1K
2K
2K
2K
Number of Bytes and Pages in the EEPROM.
Page Size
E2BYTE
E2PAGE
(Bytes)
32
ADDR[4:0]
ADDR[10:5]
32
ADDR[4:0]
ADDR[10:5]
32
ADDR[4:0]
ADDR[10:5]
32
ADDR[4:0]
ADDR[10:5]
No of Pages
32
64
64
64
12
8069C–AVR–06/08