AT52SC1283J Datasheet, PDF (34/52 Pages) ATMEL Corporation – 128-Mbit Flash + 32-Mbit/64-Mbit

28. Four-word Burst Read Waveform (Clock Latency of 4)
A
BC
CLK
CE
AVD
OE
A0-A22
VALID
I/O0-I/O15
D0 D1 D2 D3
Note:
WAIT ^{(1) HIGH Z}
1. The WAIT signal shown is for a burst configuration register of B10 and B8 = 1.
HIGH Z
29. Burst Suspend Waveform
CLK⁽²⁾
CE
AVD
I/O0-I/O15
t_CECK
t_AHCK
t_CE
t_CEAV
t_AVCK
t_ACK
t_CKAV
t_AAV
...
t_AHAV
t_CLK
t_QHCK
D0 D1
t_CKH
t_CKL
t_CKQV
D1 D2
t_CEQZ
A0-A22
OE
t_DF
t_OE
WAIT ⁽²⁾
Notes: 1. The WAIT signal (dashed line) shown is for a burst configuration register setting of B10 and B8 = 0. The WAIT Signal (solid
line) shown is for a burst configuration setting of B10 = 1 and B8 = 0.
2. During Burst Suspend, CLK signal can be held low or high.
34 AT52SC1283J/1284J [Preliminary]
3530B–STKD–2/4/05