AT52SC1283J Datasheet, PDF (1/52 Pages) ATMEL Corporation – 128-Mbit Flash + 32-Mbit/64-Mbit

Module Features
• 128-Mbit Burst/Page Flash + 32-Mbit/64-Mbit PSRAM
• Single 88-ball (8 mm x 10 mm x 1.2 mm) CBGA Package
• 1.7V to 1.95V V_CC
• 1.8V to 1.95V for V_CCQ and P_VCC
128-Mbit Flash Features
• 8M x 16 Organization
• High Performance
– Random Access Time – 70 ns, 85 ns
– Page Mode Read Time – 20 ns
– Synchronous Burst Frequency – 66 MHz
– Configurable Burst Operation
• Sector Erase Architecture
– Sixteen 4K Word Sectors with Individual Write Lockout
– Two Hundred Fifty-four 32K Word Main Sectors with Individual Write Lockout
• Typical Sector Erase Time: 32K Word Sectors – 800 ms; 4K Word Sectors – 200 ms
• Thirty-two Plane Organization, Permitting Concurrent Read in Any of the Thirty-one
Planes not Being Programmed/Erased
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation
– 30 mA Active
– 20 µA Standby
• VPP Pin for Write Protection and Accelerated Program Operations
• RESET Input for Device Initialization
• Two Protection Registers (128 Bits + 2,048 Bits)
• Common Flash Interface (CFI)
• Top and Bottom Boot Sectors
• 1.7V to 1.95V Operating Voltage
Asynchronous/Page PSRAM Features
• 32-Mbit (2M Word x 16)/64-Mbit (4M Word x 16)
• 70 ns Random Access Time
• 30 ns Page Read Cycle Time
• 1.8V to 1.95V Operating Voltage
• <10 µA Deep Standby Power
128-Mbit Flash
+ 32-Mbit/64-Mbit
PSRAM
Stack Memory
AT52SC1283J
AT52SC1284J
Preliminary
Stack Module Memory Contents
Device
AT52SC1283J
AT52SC1284J
Memory Combination
128M Flash + 32M PSRAM
128M Flash + 64M PSRAM
3530B–STKD–2/4/05