AT52BR1672 Datasheet, PDF (34/39 Pages) ATMEL Corporation – 16-megabit Flash and 2-megabit/ 4-megabit SRAM Stack Memory

Output Test Load
Timing Diagrams
Read Cycle 1^(1),(4)
ADDRESS
SCS1
t_RC
t_AA
t_ACS
t_OH
SCS2
SUB, SLB
SOE
DATA OUT
HIGH-Z
t_BA
t_OE
t_CLZ(3)
t_OLZ⁽³⁾
t_BLZ⁽³⁾
t_CHZ⁽³⁾
t_BHZ⁽³⁾
t_OHZ⁽³⁾
DATA VALID
Read Cycle 2^(1),(2),(4)
ADDRESS
DATA OUT
Read Cycle 3^(1),(2),(4)
SCS1
SUB, SLB
t_RC
t_AA
t_OH
PREVIOUS DATA
t_OH
DATA VALID
SCS2
DATA OUT
t_ACS
t ⁽³⁾
CLZ
DATA VALID
t ⁽³⁾
CHZ
Notes:
1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
status.
2. SOE = V_IL.
3. Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
34 AT52BR1672(T)/1674(T)
2604B–STKD–09/02