ATMEGA164PA_1 Datasheet, PDF (315/468 Pages) ATMEL Corporation – 8-bit Microcontroller with 16/32/64/128K Bytes In-Sytem Programmable Flash

ATmega164PA/324PA/644PA/1284P
26.9.1
Serial Programming Characteristics
For characteristics of the Serial Programming module see “SPI Timing Characteristics” on page
335.
Figure 26-12. Serial Programming Waveforms
SERIAL DATA INPUT
MSB
LSB
(MOSI)
SERIAL DATA OUTPUT
MSB
LSB
(MISO)
SERIAL CLOCK INPUT
(SCK)
SAMPLE
26.10 Programming via the JTAG Interface
26.10.1
Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,
TMS, TDI, and TDO. Control of the reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is
default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared.
Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit will be
cleared after two chip clocks, and the JTAG pins are available for programming. This provides a
means of using the JTAG pins as normal port pins in Running mode while still allowing In-Sys-
tem Programming via the JTAG interface. Note that this technique can not be used when using
the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be ded-
icated for this purpose.
During programming the clock frequency of the TCK Input must be less than the maximum fre-
quency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input
into a sufficiently low frequency.
As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.
Programming Specific JTAG Instructions
The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions
useful for programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Register is selected as path between TDI and TDO for each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be
used as an idle state between JTAG sequences. The state machine sequence for changing the
instruction word is shown in Figure 26-13 on page 316.
8152G–AVR–11/09
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