ATMEGA164PA_1 Datasheet, PDF (269/468 Pages) ATMEL Corporation – 8-bit Microcontroller with 16/32/64/128K Bytes In-Sytem Programmable Flash

ATmega164PA/324PA/644PA/1284P
24.3 Data Registers
24.3.1
The Data Registers relevant for Boundary-scan operations are:
• Bypass Register
• Device Identification Register
• Reset Register
• Boundary-scan Chain
Bypass Register
24.3.2
The Bypass Register consists of a single Shift Register stage. When the Bypass Register is
selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR
controller state. The Bypass Register can be used to shorten the scan chain on a system when
the other devices are to be tested.
Device Identification Register
Figure 24-1 shows the structure of the Device Identification Register.
Figure 24-1. The Format of the Device Identification Register
Bit
Device ID
MSB
31
28 27
Version
4 bits
Part Number
16 bits
LSB
12 11
1
0
Manufacturer ID
1
11 bits
1-bit
Version
Version is a 4-bit number identifying the revision of the component. The JTAG version number
follows the revision of the device. Revision A is 0x0, revision B is 0x1 and so on.
Part Number
The part number is a 16-bit code identifying the component. The JTAG Part Number for
ATmega164PA/324PA/644PA/1284P is listed in Table 26-6 on page 299.
Manufacturer ID
The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID
for ATMEL is listed in Table 26-6 on page 299.
24.3.3 Reset Register
The Reset Register is a test Data Register used to reset the part. Since the AVR tri-states Port
Pins when reset, the Reset Register can also replace the function of the unimplemented optional
JTAG instruction HIGHZ.
A high value in the Reset Register corresponds to pulling the external Reset low. The part is
reset as long as there is a high value present in the Reset Register. Depending on the fuse set-
tings for the clock options, the part will remain reset for a reset time-out period (refer to ”Clock
Sources” on page 31) after releasing the Reset Register. The output from this Data Register is
not latched, so the reset will take place immediately, as shown in Figure 24-2.
8152G–AVR–11/09
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