ATMEGA3250PV_14 Datasheet, PDF (310/364 Pages) ATMEL Corporation – High Endurance Non-volatile Memory segments

ATmega325P/3250P
26.9 SPI Timing Characteristics
See Figure 26-4 and Figure 26-5 for details.
Table 26-7.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SPI Timing Parameters
Description
SCK period
SCK high/low
Rise/Fall time
Setup
Hold
Out to SCK
SCK to out
SCK to out high
SS low to out
SCK period
SCK high/low⁽¹⁾
Rise/Fall time
Setup
Hold
SCK to out
SCK to SS high
SS high to tri-state
SS low to SCK
Mode
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Min
Typ
Max
See Table 17-4 on page 161
50% duty cycle
3.6
10
10
0.5 • t_sck
ns
10
10
15
4 • t_ck
2 • t_ck
1.6
µs
10
t_ck
15
ns
20
10
20 • t_ck
Notes: 1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t_CLCL for f_CK < 12 MHz
- 3 t_CLCL for f_CK > 12 MHz
Figure 26-4. SPI Interface Timing Requirements (Master Mode)
SS
6
1
SCK
(CPOL = 0)
2
2
SCK
(CPOL = 1)
45
3
MISO
(Data Input)
MSB
...
7
LSB
8
MOSI
(Data Output)
MSB
...
LSB
8023F–AVR–07/09
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