ATMEGA3250PV_14 Datasheet, PDF (162/364 Pages) ATMEL Corporation – High Endurance Non-volatile Memory segments

ATmega325P/3250P
17.5.2
Table 17-4. Relationship Between SCK and the Oscillator Frequency (Continued)
SPI2X
1
1
1
1
SPR1
0
0
1
1
SPR0
0
1
0
1
SCK Frequency
f_osc/2
f_osc/8
f_osc/32
f_osc/64
SPSR – SPI Status Register
Bit
7
6
5
4
3
2
1
0
0x2D (0x4D)
SPIF
WCOL
–
–
–
–
–
SPI2X
SPSR
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bit 5:1 – Res: Reserved Bits
These bits are reserved and will always read as zero.
17.5.3
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see Table 17-4 on page 161). This means that the minimum SCK period will
be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to
work at f_osc/4 or lower.
The SPI interface on the ATmega325P/3250P is also used for program memory and EEPROM
downloading or uploading. See page 285 for serial programming and verification.
SPDR – SPI Data Register
Bit
0x2E (0x4E)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
MSB
LSB
SPDR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
Undefined
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shift Register Receive buffer to be read.
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