U6815BM_09 Datasheet, PDF (3/14 Pages) ATMEL Corporation – Dual Hex DMOS Output Driver with Serial Input Control

U6815BM
2. Pin Configuration
Figure 2-1.
Pinning SO28
HS6 LS6 DI CLK CS GND GND GND GND VCC DO INH LS1 HS1
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Lead frame
U6815BM
1
2
3
4
5
6
7
8
9
10 11 12 13 14
LS5 HS5 HS4 LS4 VS GND GND GND GND VS LS3 HS3 HS2 LS2
Table 2-1. Pin Description
Pin
Symbol Function
1
LS5
Low-side driver output 5, power-MOS open drain with internal reverse diode, overvoltage protection by
active zenering, short-circuit protection, diagnosis for short and open load
2
HS5
High-side driver output 5, power-MOS open drain with internal reverse diode, overvoltage protection by
active zenering, short-circuit protection, diagnosis for short and open load
3
HS4
High-side driver output 4 (see pin 2)
4
LS4
Low-side driver output 4 (see pin 1)
5
VS
Power supply output stages HS4, HS5, HS6, internal supply; external connection to pin 10 necessary
6, 7, 8, 9
GND
Ground, reference potential, internal connection to pin 20 to 23, cooling tab
10
VS
Power supply output stages HS1, HS2 and HS3
11
LS3
Low-side driver output 3 (see pin 1)
12
HS3
High-side driver output 3 (see pin 2)
13
HS2
High-side driver output 2 (see pin 2)
14
LS2
Low-side driver output 2 (see pin 1)
15
HS1
High-side driver output 1 (see pin 2)
16
LS1
Low-side driver output 1 (see pin 1)
17
INH
Inhibit input, 5-V logic input with internal pull down, low = standby, high = normal operating
Serial data output, 5-V CMOS logic level tristate output for output (status) register data, sends 16-bit
18
DO
status information to the microcontroller (LSB is transferred first). Output will remain tristated unless
device is selected by CS = low, therefore, several ICs can operate on one data output line only.
19
VCC
Logic supply voltage (5V)
20, 21, 22, 23
GND
Ground (see pins 6 to 9)
24
CS
Chip select input, 5-V CMOS logic level input with internal pull-up, low = serial communication is
enabled, high = disabled
25
CLK
Serial clock input, 5-V CMOS logic level input with internal pull-down, controls serial data input
interface and internal shift register (f_max = 2 MHz)
26
DI
Serial data input, 5-V CMOS logic level input with internal pull-down, receives serial data from the
control device, DI expects a 16-bit control word with LSB being transferred first
27
LS6
Low-side driver output 6 (see pin 1)
28
HS6
High-side driver output 6 (see pin 2)
3
4545D–BCD–04/09