ATC18RHA_08 Datasheet, PDF (3/22 Pages) ATMEL Corporation – Rad. Hard 0.18 μm CMOS Cell-based ASIC for Space Use

Clusters
ATC18RHA
The periphery of the chip (pad ring) can be split into several I/O segments (I/O clusters) which
can be supplied at different voltages (ie “n” clusters at 2.5V and “m” clusters at 3.3V). Some
clusters can be unpowered while others are active.
A specific Power control line is distributed inside the cluster to be able to force all the I/Os of the
cluster in tristate mode whatever their initial state is (ie: an output only buffer will also be turned
to HiZ mode).
This Power Control line can be driven in two ways:
• Cold Sparing mode: the Power control line is active when VCCB is “off” (case of VCCB
Power Supply Pad including a Power Control feature).
• Hot Swap mode: a specific pad in the cluster is dedicated to Power Control. When this pad
is left open (driven to “0” by an internal pull-down) the Power Control line is activated.
ESD Protection
The introduction of a multiple supply architecture increases the sensitivity to Electro-Static Dis-
charges. In ATC18RHA periphery, the VCCB,VSSB supplies are isolated from VCC, VSS
supplies and furthermore when making clusters, the VCCB supply rail is split into several
segments.
A solution to improve ESD immunity consists in adding discharge conduction paths between
supply rails. To implement this solution some specific cells must be inserted in the Pad Ring.
Two kinds of cells are used:
• Back to Back Diodes between VSSB and VSS
• Grounded N-Gates between two VCCB segments
Some ESD cells are “pad count” transparent (implemented in the Die Corners) but others must
be taken into account in the Pad Ring definition (each ESD cell has the size of a standard pad).
Double Pad Ring
In the double pad ring configuration, all core power supply pads must be moved to the inner ring
and PV18IxxZ pads must be replaced by PV18IDxxZ pads. Therefore, there must be no
PV18ID00Z or PV18ID18Z pads left on the outer ring .
The number of pads on the inner ring will be tailored to the actual need of each design.
These core supplies are automatically routed to the inner ring. As long as the double pad ring
configuration is used only for core supply pads, the designs are produceable to space quality
levels.
During the detailed feasibility study, an investigation will be conducted to evaluate if additional
pads, and how many, can be added to the inner ring to be used as pure CMOS IO and their
power supplies, and still be produced to space quality. Anyhow, the resulting total number of
pads on the inner ring must not go above the maximum number given in the table 4.
Warning: there is no means to have any LVDS IO and their power supplies moved to the inner
ring.
Pad Site and Pad Pitch In the ATC18RHA95 family the minimum Pad Width and Pad Pitch are 95µm.
Case of Differential Pads
• LVDS transmitter: width= 3x95µm and pitch= 190µm
• LVDS Receiver and LVPECL Receiver : width= 2x95µm and pitch=95µm
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4261F–AERO–08/08