ATC18RHA_08 Datasheet, PDF (1/22 Pages) ATMEL Corporation – Rad. Hard 0.18 μm CMOS Cell-based ASIC for Space Use

Features
• Comprehensive Library of Standard Logic and I/O Cells
• ATC18RHA Core pads Designed to Operate with VDD = 1.8V +/- 0.15V as Main Condition
• IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V and 2.5 +/- 0.25V Environments
• Memory Cells Compiled or synthesized to the Requirements of the Design
• EDAC Library
• Cold Sparing Buffers
• High Speed LVDS Buffers (655Mbps)
• PCI Buffers
• Predefined Die Sizes to Accommodate Standardized Packages and ESA (European
Space Agency) Multi-project Wafer Services
• MQFP Package Up to 352 Pins (336 Signal Pins)
• MCGA Packages Up to 625 Pins (575 Signal Pins)
• ESD better than 2000V for IO33 and better than 1000V for PLL
• No single event latch-up below a LET threshold of 80 Mev/mg/cm² at ambient
temperature
• SEU hardened flip-flops
• Tested up to a total dose of 300 krads (Si) according to Mil Std 883 Test Method 1019
• Quality Grades: QML-Q and QML-V with 5962-06B02, ESCC 9000
Description
The ATC18RHA is fabricated on a proprietary 0.18 µm, five-metal-layers CMOS pro-
cess intended for use with a supply voltage of 1.8V ± 0.15V.
The Atmel cell libraries and memory compilers have been designed and or character-
ized in order to be compatible with each other. Simulation representations exist for
three types of operating conditions. They correspond to three characterization condi-
tion sets defined as follows:
• MIN conditions:
– – TJ = -55°C
– – VDD (cell) = 1.95V
– – Process = fast (0.95)
• TYP conditions:
– – TJ = +25°C
– – VDD (cell) = 1.8V
– – Process = typical (1)
• MAX conditions:
– – TJ = +125°C
– – VDD (cell) = 1.65V
– – Process = slow (1.1)
Rad. Hard
0.18 µm CMOS
Cell-based ASIC
for Space Use
ATC18RHA
4261F–AERO–08/08