AT28BV64 Datasheet, PDF (3/8 Pages) ATMEL Corporation – 64K 8K x 8 Battery-Voltage CMOS E2PROM

AT28BV64
Device Operation
READ: The AT28BV64 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in a high im-
pedance state whenever CE or OE is high. This dual line
control gives designers increased flexibility in preventing
bus contention.
BYTE WRITE: Writing data into the AT28BV64 is similar
to writing into a Static RAM. A low pulse on the WE or CE
input with OE high and CE or WE low (respectively) initi-
ates a byte write. The address location is latched on the
falling edge of WE (or CE); the new data is latched on the
rising edge. Internally, the device performs a self-clear be-
fore write. Once a byte write has been started, it will auto-
matically time itself to completion. Once a programming
operation has been initiated and for the duration of tWC, a
read operation will effectively be a polling operation.
READY/BUSY: Pin 1 is an open drain READY/BUSY
output that can be used to detect the end of a write cycle.
RDY/BUSY is actively pulled low during the write cycle
and is released at the completion of the write. The open
drain connection allows for OR-tying of several devices to
the same RDY/BUSY line.
DATA POLLING: The AT28BV64 provides DATA
POLLING to signal the completion of a write cycle. During
a write cycle, an attempted read of the data being written
results in the complement of that data for I/O7 (the other
outputs are indeterminate). When the write cycle is fin-
ished, true data appears on all outputs.
WRITE PROTECTION: Inadvertent writes to the device
are protected against in the following ways. (a) VCC
sense— if VCC is below 1.8V (typical) the write function is
inhibited. (b) VCC power on delay— once VCC h a s
reached 2.0V the device will automatically time out 10 ms
(typical) before allowing a byte write. (c) Write Inhibit—
holding any one of OE low, CE high or WE high inhibits
byte write cycles.
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