AT24C1024_14 Datasheet, PDF (3/19 Pages) ATMEL Corporation – Schmitt Triggers, Filtered Inputs for Noise Suppression

AT24C1024
Pin Description
Memory
Organization
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.
DEVICE/ADDRESSES (A1): The A1 pin is a device address input that can be hardwired or
left not connected for hardware compatibility with other AT24Cxx devices. When the A1 pin is
hardwired, as many as two 1024K devices may be addressed on a single bus system (device
addressing is discussed in detail under the Device Addressing section). If the A1 pin is left
floating, the A1 pin will be internally pulled down to GND if the capacitive coupling to the circuit
board V_CC plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting the A1 pin to
GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal
write operations. When WP is connected high to V_CC, all write operations to the memory are
inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the
capacitive coupling to the circuit board V_CC plane is <3 pF. If coupling is >3 pF, Atmel recom-
mends connecting the pin to GND. Switching WP to V_CC prior to a write operation creates a
software write-protect function.
AT24C1024, 1024K SERIAL EEPROM: The 1024K is internally organized as 512 pages of
256 bytes each. Random word addressing requires a 17-bit data word address.
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