AT24C1024_14 Datasheet, PDF (1/19 Pages) ATMEL Corporation – Schmitt Triggers, Filtered Inputs for Noise Suppression

Features
• Low-voltage Operation
– 2.7 (V_CC = 2.7V to 5.5V)
• Internally Organized 131,072 x 8
• Two-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 400 kHz (2.7V) and 1 MHz (5V) Clock Rate
• Write Protect Pin for Hardware and Software Data Protection
• 256-byte Page Write Mode (Partial Page Writes Allowed)
• Random and Sequential Read Modes
• Self-timed Write Cycle (5 ms Typical)
• High Reliability
– Endurance: 100,000 Write Cycles/Page
– Data Retention: 40 Years
• 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead LAP and 8-lead SAP Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Die
Description
The AT24C1024 provides 1,048,576 bits of serial electrically erasable and program-
mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The
device’s cascadable feature allows up to two devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space-saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead Leadless Array (LAP) and 8-
lead SAP packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V)
versions.
Two-wire Serial
EEPROM
1M (131,072 x 8)
AT24C1024⁽¹⁾
Note:
1. Not recommended for
new design; please
refer to AT24C1024B
datasheet.
Table 1. Pin Configurations
Pin Name
Function
A1
Address Input
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
NC
No Connect
8-lead SOIC
NC 1
A1 2
NC 3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
8-lead PDIP
NC 1
A1 2
NC 3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
8-lead Leadless Array
VCC 8
WP 7
SCL 6
SDA 5
1 NC
2 A1
3 NC
4 GND
Bottom View
8-lead SAP
VCC 8
WP 7
SCL 6
SDA 5
1 NC
2 A1
3 NC
4 GND
Bottom View
Rev. 1471O–SEEPR–3/07
1