ATA5723 Datasheet, PDF (28/46 Pages) ATMEL Corporation – UHF ASK/FSK Receiver

Table 11-10. Effect of the Configuration Word Lim_min
Lim_min⁽¹⁾ (Lim_min < 10 is not Applicable)
Lower Limit Value for Bit Check
Lim_min5
0
Lim_min4
0
Lim_min3
1
Lim_min2
0
Lim_min1
1
Lim_min0
0
(T_{Lim_min} = Lim_min × XLim × T_Clk)
10
0
0
1
0
1
1
11
0
0
1
1
0
0
12
..
..
..
..
..
..
21 (default, BR_Range0)
0
1
0
1
0
1
(T_{Lim_min} = 347 µs for f_RF = 868.3 MHz
T_{Lim_min} = 347 µs for f_RF = 433.92 MHz
T_{Lim_min} = 342 µs for f_RF = 315 MHz)
..
..
..
..
..
..
1
1
1
1
0
1
61
1
1
1
1
1
0
62
1
1
1
1
1
1
63
Note: 1. Lim_min is also used to determine the margins of the data clock control logic (see Section 9. “Data Clock” on page 19).
Table 11-11. Effect of the Configuration Word Lim_max
Lim_max⁽¹⁾ (Lim_max < 12 is not applicable)
Upper Limit Value for Bit Check
Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0 (TLim_max = (Lim_max – 1) × XLim × T_Clk)
0
0
1
1
0
0
12
0
0
1
1
0
1
13
0
0
1
1
1
0
14
..
..
..
..
..
..
41 (default, BR_Range0)
1
0
1
0
0
1
(T_{Lim_max} = 661 µs for f_RF = 868.3 MHz
T_{Lim_max} = 662 µs for f_RF = 433.92 MHz
T_{Lim_max} = 652 µs for f_RF = 315 MHz)
..
..
..
..
..
..
1
1
1
1
0
1
61
1
1
1
1
1
0
62
1
1
1
1
1
1
63
Note: 1. Lim_max is also used to determine the margins of the data clock control logic (see Section 9. “Data Clock” on page 19).
28 ATA5723/ATA5724/ATA5728
9106E–RKE–07/08