AT49SN12804 Datasheet, PDF (28/41 Pages) ATMEL Corporation – 128-megabit (8M x 16) Burst/Page Mode 1.8-volt Flash Memory

AC Asynchronous Read Timing Characteristics
Symbol
Parameter
Min
Max
Units
t_ACC1
Access, AVD To Data Valid
70
ns
t_ACC2
Access, Address to Data Valid
70
ns
t_CE
Access, CE to Data Valid
70
ns
t_OE
OE to Data Valid
20
ns
t_AHAV
Address Hold from AVD
9
ns
t_AVLP
AVD Low Pulse Width
10
ns
t_AVHP
AVD High Pulse Width
10
ns
t_AAV
Address Valid to AVD
7
ns
t_DF
CE, OE High to Data Float
25
ns
t_OH
Output Hold from OE, CE or Address, Whichever Occurred First
ns
t_RO
RESET to Output Delay
150
ns
AVD Pulsed Asynchronous Read Cycle Waveform⁽¹⁾⁽²⁾
tCE
CE
I/O0-I/O15
tACC2
tDF
DATA VALID
tDF
A2 -A22
tAAV
tAHAV
tACC2
A0 -A1
tAAV
tAHAV
(1)
AVD
tAVHP
tAVLP
tACC1
OE
tOE
tRO
RESET
Notes: 1. After the high-to-low transition on AVD, AVD may remain low as long as the address is stable.
2. CLK may be static high or static low.
Asynchronous Read Cycle Waveform^(1)(2)(3)(4)
A0 - A22
t_RC
ADDRESS VALID
CE
t_CE
OE
t_OE
t_ACC2
t_DF
t_OH
RESET
t_RO
I/O0 - I/O15
HIGH Z
OUTPUT
VALID
Notes:
1. CE may be delayed up to t_ACC - t_CE after the address transition without impact on t_ACC.
2. OE may be delayed up to t_CE - t_OE after the falling edge of CE without impact on t_CE or by t_ACC - t_OE after an address change
without impact on t_ACC.
3. t_DF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. AVD and CLK should be tied low.
28 AT49SN/SV12804 [Preliminary]
3314A–FLASH–4/04