ATMEGA329V_14 Datasheet, PDF (262/392 Pages) ATMEL Corporation – High Performance, Low Power Atmel

Table 25-5. Boundary-scan Signals for the ADC⁽¹⁾ (Continued)
Signal Name
NEGSEL_2
Direction as seen
from the ADC
Input
Description
Input Mux for negative input for differential
signal, bit 2
Recommended
Input when not
in use
0
Output Values when
recommended inputs are used,
and CPU is not using the ADC
0
NEGSEL_1 Input
Input Mux for negative input for differential
0
0
signal, bit 1
NEGSEL_0 Input
Input Mux for negative input for differential
0
0
signal, bit 0
PASSEN
Input
Enable pass-gate of differential amplifier.
1
1
PRECH
Input
Precharge output latch of comparator.
1
1
(Active low)
SCTEST
Input
Switch-cap TEST enable. Output from
0
0
differential amplifier send out to Port Pin
having ADC_4
ST
Input
Output of differential amplifier will settle
0
0
faster if this signal is high first two ACLK
periods after AMPEN goes high.
VCCREN Input
Selects Vcc as the ACC reference voltage.
0
0
Notes:
1. Incorrect setting of the switches in Figure 25-9 will make signal contention and may damage the part. There are several input
choices to the S&H circuitry on the negative input of the output comparator in Figure 25-9. Make sure only one path is
selected from either one ADC pin, Bandgap reference source, or Ground.
If the ADC is not to be used during scan, the recommended input values from Table 25-5 should
be used. The user is recommended not to use the differential amplifier during scan. Switch-Cap
based differential amplifier require fast operation and accurate timing which is difficult to obtain
when used in a scan chain. Details concerning operations of the differential amplifier is therefore
not provided.
The AVR ADC is based on the analog circuitry shown in Figure 25-9 with a successive approxi-
mation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is
usually to ensure that an applied analog voltage is measured within some limits. This can easily
be done without running a successive approximation algorithm: apply the lower limit on the digi-
tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit
on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following
• The port pin for the ADC channel in use must be configured to be an input with pull-up
disabled to avoid signal contention.
• In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal
low (Sample mode).
262 ATmega329/3290/649/6490
2552K–AVR–04/11