AT89S51_14 Datasheet, PDF (26/31 Pages) ATMEL Corporation – 4K Bytes of In-System Programmable (ISP) Flash Memory

30. Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for V_CC = 4.0V to 5.5V and Load Capacitance = 80 pF.
12 MHz Osc
Variable Oscillator
Symbol
Parameter
Min
Max
Min
Max
t_XLXL
t_QVXH
t_XHQX
t_XHDX
t_XHDV
Serial Port Clock Cycle Time
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
1.0
12 t_CLCL
700
10 t_CLCL-133
50
2 t_CLCL-80
0
0
700
10 t_CLCL-133
31. Shift Register Mode Timing Waveforms
INSTRUCTION
ALE
CLOCK
WRITE TO SBUF
OUTPUT DATA
CLEAR RI
0
1
2
3
4
5
6
7
8
t_QVXH
0
t_XHDV
VALID
t_XLXL
t_XHQX
1
VALID
2
t_XHDX
VALID
3
VALID
4
VALID
5
VALID
6
7
SET TI
VALID
VALID
INPUT DATA
SET RI
Units
µs
ns
ns
ns
ns
32. AC Testing Input/Output Waveforms⁽¹⁾
Note:
V_CC - 0.5V
0.45V
0.2 V_CC + 0.9V
TEST POINTS
0.2 V_CC - 0.1V
1. AC Inputs during testing are driven at V_CC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at V_IH
min. for a logic 1 and V_IL max. for a logic 0.
33. Float Waveforms⁽¹⁾
Note:
V_LOAD
V
+
LOAD
0.1V
V _LOAD ^{- 0.1V}
Timing Reference
Points
V _OL ^{- 0.1V}
V _OL ^{+ 0.1V}
1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to
float when a 100 mV change from the loaded V_OH/V_OL level occurs.
26 AT89S51
2487D–MICRO–6/08