ATA6602 Datasheet, PDF (256/362 Pages) ATMEL Corporation – Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

Figure 4-95. Formats and States in the Slave Transmitter Mode
Reception of the own
slave address and one or
S
SLA
R
A
DATA
A
more data bytes
$A8
$B8
Arbitration lost as master
and addressed as slave
A
DATA
A
P or S
$C0
$B0
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
A
All 1's P or S
$C8
4.19.8.5
From master to slave
From slave to master
DATA
n
Any number of data bytes
A
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
Miscellaneous States
There are two status codes that do not correspond to a defined TWI state (see Table 4-94).
Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not
set. This occurs between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte,
or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the
TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the
TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in
TWCR are affected). The SDA and SCL lines are released, and no STOP condition is
transmitted.
Table 4-94. Miscellaneous States
Status Code
(TWSR)
Status of the 2-wire Serial
Prescaler Bits Bus and 2-wire Serial
are 0
Interface Hardware
0xF8
No relevant state information
available; TWINT = “0”
0x00
Bus error due to an illegal
START or STOP condition
Application Software Response
To TWCR
To/from TWDR STA STO TWINT TWEA Next Action Taken by TWI Hardware
No TWDR action
No TWCR action
Wait or proceed current transfer
Only the internal hardware is affected, no STOP
No TWDR action 0
1
1
X condition is sent on the bus. In all cases, the bus
is released and TWSTO is cleared.
256 ATA6602/ATA6603
4921C–AUTO–01/07