ATA6602 Datasheet, PDF (194/362 Pages) ATMEL Corporation – Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

4.17.2.3
4.17.2.4
External Clock
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to Figure 4-70 on page 192 for details.
External clock input from the XCKn pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency
is limited by the following equation:
f_XCK
<
-^f-^O----^S---^C--
4
Note that f_osc depends on the stability of the system clock source. It is therefore recommended to
add some margin to avoid possible loss of data due to frequency variations.
Synchronous Clock Operation
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxDn) is sampled at the
opposite XCKn clock edge of the edge the data output (TxDn) is changed.
Figure 4-71. Synchronous Mode XCKn Timing
UCPOL = 1
XCK
RxD / TxD
UCPOL = 0
XCK
Sample
RxD / TxD
Sample
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is
used for data change. As Figure 4-71 shows, when UCPOLn is zero the data will be changed at
rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed
at falling XCKn edge and sampled at rising XCKn edge.
194 ATA6602/ATA6603
4921C–AUTO–01/07