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| ATMEGA48_14 Datasheet, PDF (252/377 Pages) ATMEL Corporation – High endurance non-volatile memory segments | |||
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ATmega48/88/168
and ADC5) will only affect the conversion on ADC4 and ADC5 and not the other ADC
channels.
Figure 24-9. ADC power connections.
PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5
24.6.3
ADC accuracy definitions
An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps
(LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
Several parameters describe the deviation from the ideal behavior:
⢠Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at
0.5LSB). Ideal value: 0LSB
2545TâAVRâ05/11
252
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