AT32UC3B0512_1 Datasheet, PDF (244/676 Pages) ATMEL Corporation – 32-bit AVR® Microcontroller

AT32UC3B
19.13.6.2
Clock Synchronization in Write Mode
The clock is tied low if the shift register and the RHR is full. If a STOP or REPEATED_START
condition was not detected, it is tied low until RHR is read.
Figure 19-28 on page 244 describes the clock synchronization in Read mode.
Figure 19-28. Clock Synchronization in Write Mode
TWCK
TWD
CLOCK is tied low by the TWI as long as RHR is full
S SADR W A DATA0 A DATA1
A DATA2 NA S ADR
TWI_RHR
DATA0 is not read in the RHR
DATA1
DATA2
SCLWS
RXRDY
SVACC
SVREAD
TXCOMP
As soon as a START is detected
SCL is stretched on the last bit of DATA1
Rd DATA0
Rd DATA1 _{Rd DATA2}
Notes:
1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mecha-
nism is finished.
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