ATMEGA3290V_14 Datasheet, PDF (243/392 Pages) ATMEL Corporation – High Endurance Non-volatile Memory Segments

ATmega329/3290/649/6490
23.4.4 LCDCCR – LCD Contrast Control Register
Bit
7
6
5
4
3
2
1
0
(0xE7)
LCDDC2 LCDDC1 LCDDC0
–
LCDCC3 LCDCC2 LCDCC1 LCDCC0 LCDCCR
Read/Write
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bits 7:5 – LCDDC2:0: LDC Display Configuration
The LCDDC2:0 bits determine the amount of time the LCD drivers are turned on for each volt-
age transition on segment and common pins. A short drive time will lead to lower power
consumption, but displays with high internal resistance may need longer drive time to achieve
satisfactory contrast. Note that the drive time will never be longer than one half prescaled LCD
clock period, even if the selected drive time is longer. When using static duty or blanking, drive
time will always be one half prescaled LCD clock period.
New values take effect immediately, and can cause small glitches in the display output. This can
be avoided by setting the LCDBL in LCDCRA, and wait to the next start of frame before chang-
ing LCDDC2:0.
Table 23-7. LCD Display Configuration
LCDDC2
LCDDC1
LCDDC0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Nominal drive time
300µs
70µs
150µs
450µs
575µs
850µs
1150µs
50% of clk_{LCD_PS}
Note: The drive time will be longer dependent on oscillator startup time.
• Bit 4 – Reserved Bit
This bit is reserved in the ATmega329/3290/649/6490 and will always read as zero.
• Bits 3:0 – LCDCC3:0: LCD Contrast Control
The LCDCC3:0 bits determine the maximum voltage V_LCD on segment and common pins. The
different selections are shown in Table 23-8. New values take effect every beginning of a new
frame.
Table 23-8.
LCDCC3
0
0
0
0
LCD Contrast Control
LCDCC2
LCDCC1
0
0
0
0
0
1
0
1
LCDCC0
0
1
0
1
Maximum Voltage V_LCD
2.60
2.65
2.70
2.75
2552K–AVR–04/11
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