PC8260 Datasheet, PDF (24/53 Pages) ATMEL Corporation – PowerPC-based Communications Processors

Table 4. External Signals (Continued)
Pin
Signal Name
PSDVAL
60x Data Valid
TA
Transfer Acknowledge
TEA
GBL
IRQ1
Transfer Error
Acknowledge
Global
CI
BADDR29
IRQ2
Interrupt Request 1
Cache Inhibit
Burst Address 29
WT
BADDR30
IRQ3
Interrupt Request 2
Write Through
Burst Address 30
Interrupt Request 3
Type
I/O
I/O
I/O
I/O
I
O
Description
Assertion of the PSDVAL pin indicates that a data beat is valid on the
data bus. The difference between the TA pin and the PSDVAL pin is that
the TA pin is asserted to indicate 60x data transfer terminations, while
the PSDVAL signal is asserted with each data beat movement. Thus,
always when TA is asserted, PSDVAL will be asserted, but, when
PSDVAL is asserted, TA is not necessarily asserted. For example, when
a double-double word (2x64 bits) transfer is initiated by the SDMA to a
memory device that has 32 bits port size, PSDVAL will be asserted 3
times without TA and, finally, both pins will be asserted to terminate the
transfer.
Assertion of theTA pin indicates that a 60x data beat is valid on the data
bus. For 60x single beat transfers, assertion of this pin indicates the
termination of the transfer. For 60x burst transfers, this pin will be
asserted four times to indicate the transfer of four data beats, with the
last assertion indicating the termination of the burst transfer.
Assertion of this pin indicates a bus error. 60x masters within the
PowerQUICC II monitor the state of this pin. PowerQUICC II’s internal
bus monitor may assert this pin if it has identified a 60x transfer that is
hung.
When a 60x master within the chip initiates a bus transaction it drives
this pin. When an external 60x master initiates a bus transaction, it
should drive this pin. Assertion of this pin indicates that the transfer is
global and it should be snooped by caches in the system. The
PowerQUICC II data cache monitors the state of this pin.
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
This pin is an output pin. It is used for L2 cache control. For each
BADDR29 PowerQUICC II 60x transaction initiated in the core, the state
of this pin indicates if this transaction should be cached or not. Assertion
of the CI pin indicates that the transaction should not be cached.
O There are five burst address output pins. These pins are outputs of the
60x memory controller. These pins are used in external master
configuration and are connected directly to memory devices controlled
by PowerQUICC II memory controller.
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
O Output used for L2 cache control. For each core initiated PowerQUICC II
60x transaction, the state of this pin indicates if the transaction should be
cached using write-through or copy-back mode. Assertion of WT
indicates that the transaction should be cached using the write-through
mode.
O There are five burst address output pins. These pins are outputs of the
60x memory controller. These pins are used in external master
configuration and are connected directly to memory devices controlled
by PowerQUICC II’s memory controller.
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
24 PC8260 PowerQUICC II
2131B–HIREL–02/03