AT43USB353M_04 Datasheet, PDF (24/95 Pages) ATMEL Corporation – Low Cost Full-speed USB Microcontroller with Embedded Hub, ADC and PWM

External Interrupts
The external interrupts are triggered by the INT0 and INT1 pins. Observe that, if enabled, the
INT0/INT1 interrupt will trigger even if the INT0/INT1 pin is configured as an output. This fea-
ture provides a way of generating a software interrupt. The external interrupts can be triggered
by a falling or rising edge or a low level. This is set up as indicated in the specification for the
MCU Control Register (MCUCR) and the Interrupt Sense Control Register (ISCR). When
INT0/INT1 is enabled and is configured as level triggered, the interrupt will trigger as long as
the pin is held low. INT0/INT1 is set up as described in the specification for the MCU Control
Register (MCUCR).
Interrupt
Response Time
The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum.
4 clock cycles after the interrupt flag has been set, the program vector address for the actual
interrupt handling routine is executed. During this 4 clock cycle period, the Program Counter (2
bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2. The vector is nor-
mally a jump to the interrupt routine, and this jump takes 3 clock cycles. If an interrupt occurs
during execution of a multi-cycle instruction, this instruction is completed before the interrupt is
served.
A return from an interrupt handling routine (same as for a subroutine call routine) takes 4 clock
cycles. During these 4 clock cycles, the Program Counter (2 bytes) is popped back from the
Stack, the Stack Pointer is incremented by 2, and the I flag in SREG is set. When the AVR
exits from an interrupt, it will always return to the main program and execute one more instruc-
tion before any pending interrupt is served.
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