ATA6612 Datasheet, PDF (230/364 Pages) ATMEL Corporation – Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

6.19 2-wire Serial Interface
6.19.1 Features
• Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed
• Both Master and Slave Operation Supported
• Device can Operate as Transmitter or Receiver
• 7-bit Address Space Allows up to 128 Different Slave Addresses
• Multi-master Arbitration Support
• Up to 400 kHz Data Transfer Speed
• Slew-rate Limited Output Drivers
• Noise Suppression Circuitry Rejects Spikes on Bus Lines
• Fully Programmable Slave Address with General Call Support
• Address Recognition Causes Wake-up When AVR is in Sleep Mode
6.19.2
2-wire Serial Interface Bus Definition
The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The
TWI protocol allows the systems designer to interconnect up to 128 different devices using only
two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-
ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All
devices connected to the bus have individual addresses, and mechanisms for resolving bus
contention are inherent in the TWI protocol.
Figure 6-77. TWI Bus Interconnection
V_CC
Device 1
Device 2
Device 3 ........ Device n
R1
R2
6.19.2.1
SDA
SCL
TWI Terminology
The following definitions are frequently encountered in this section.
Table 6-87.
Term
Master
Slave
Transmitter
Receiver
TWI Terminology
Description
The device that initiates and terminates a transmission. The Master also generates the
SCL clock.
The device addressed by a Master.
The device placing data on the bus.
The device reading data from the bus.
The PRTWI bit in “Power Reduction Register - PRR” on page 66 must be written to zero to
enable the 2-wire Serial Interface.
230 ATA6612/ATA6613
9111E–AUTO–07/08