ATA6612 Datasheet, PDF (175/364 Pages) ATMEL Corporation – Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

ATA6612/ATA6613
Table 6-60 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase cor-
rect PWM mode.
Table 6-60.
COM2A1
0
0
1
1
Compare Output Mode, Phase Correct PWM Mode⁽¹⁾
COM2A0 Description
0
Normal port operation, OC2A disconnected.
1
WGM22 = 0: Normal Port Operation, OC2A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
0
Clear OC2A on Compare Match when up-counting. Set OC2A on
Compare Match when down-counting.
1
Set OC2A on Compare Match when up-counting. Clear OC2A on
Compare Match when down-counting.
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 171 for more details.
• Bits 5:4 – COM2B1:0: Compare Match Output B Mode
These bits control the Output Compare pin (OC2B) behavior. If one or both of the
COM2B1:0 bits are set, the OC2B output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OC2B pin must be set in order to enable the output driver.
When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the
WGM22:0 bit setting. Table 6-61 shows the COM2B1:0 bit functionality when the WGM22:0
bits are set to a normal or CTC mode (non-PWM).
Table 6-61.
COM2B1
0
0
1
1
Compare Output Mode, non-PWM Mode
COM2B0 Description
0
Normal port operation, OC2B disconnected.
1
Toggle OC2B on Compare Match
0
Clear OC2B on Compare Match
1
Set OC2B on Compare Match
Table 6-62 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM
mode.
Table 6-62.
COM2B1
0
0
1
1
Compare Output Mode, Fast PWM Mode⁽¹⁾
COM2B0 Description
0
Normal port operation, OC2B disconnected.
1
Reserved
0
Clear OC2B on Compare Match, set OC2B at TOP
1
Set OC2B on Compare Match, clear OC2B at TOP
Note:
1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 171 for more details.
9111E–AUTO–07/08
175