ATMEGA645V_14 Datasheet, PDF (228/362 Pages) ATMEL Corporation – High Endurance Non-volatile Memory Segments

ATmega325/3250/645/6450
25.5.2
software must write this bit to the desired value twice within four cycles to change its value. Note
that this bit must not be altered when using the On-chip Debug system.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to
one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.
MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit
7
6
5
4
3
2
1
0
0x34 (0x54)
–
–
–
JTRF WDRF BORF EXTRF PORF MCUSR
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
See Bit Description
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
25.6
Boundary-scan Chain
The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connection.
25.6.1
Scanning the Digital Port Pins
Figure 25-3 shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The
cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn – function, and a
bi-directional pin cell that combines the three signals Output Control – OCxn, Output Data –
ODxn, and Input Data – IDxn, into only a two-stage Shift Register. The port and pin indexes are
not used in the following description
The Boundary-scan logic is not included in the figures in the Data Sheet. Figure 25-4 shows a
simple digital port pin as described in the section “I/O-Ports” on page 60. The Boundary-scan
details from Figure 25-3 replaces the dashed box in Figure 25-4.
When no alternate port function is present, the Input Data – ID – corresponds to the PINxn Reg-
ister value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output
Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – cor-
responds to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in Figure 25-4 to make the
scan chain read the actual pin value. For Analog function, there is a direct connection from the
external pin to the analog circuit, and a scan chain is inserted on the interface between the digi-
tal logic and the analog circuitry.
2570N–AVR–05/11
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