ATMEGA645V_14 Datasheet, PDF (210/362 Pages) ATMEL Corporation – High Endurance Non-volatile Memory Segments

ATmega325/3250/645/6450
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last
transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).
Ideal value: 0 LSB
Figure 23-11. Gain Error
Output Code
Gain
Error
Ideal ADC
Actual ADC
V_REF Input Voltage
• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum
deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0
LSB.
Figure 23-12. Integral Non-linearity (INL)
Output Code
Ideal ADC
Actual ADC
V_REF Input Voltage
2570N–AVR–05/11
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