SAMD20G_14 Datasheet, PDF (227/676 Pages) ATMEL Corporation – SMART ARM-Based Microcontroller

18.8.5 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
18.8.5.1 Mode 0
Name:
Offset:
Reset:
Property:
INTENSET
0x07
0x00
Write-Protected
Bit
7
6
5
4
3
2
1
0
OVF
SYNCRDY
CMP0
Access
R/W
R/W
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z Bit 7 – OVF: Overflow Interrupt Enable
0: The overflow interrupt is disabled.
1: The overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt.
z Bit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The synchronization ready interrupt is disabled.
1: The synchronization ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the Synchronization
Ready interrupt.
z Bits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 0 – CMP0: Compare 0 Interrupt Enable
0: The compare 0 interrupt is disabled.
1: The compare 0 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Compare 0 Interrupt Enable bit and enable the Compare 0 interrupt.
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129L–SAM-D20_datasheet–09/2014
227