ATAM510 Datasheet, PDF (22/72 Pages) ATMEL Corporation – MARC4 4-bit MTP Universal Microcontroller

Figure 3-1. Example of I/O Addressing
Module ASW
Auxiliary Switch
Module
Module M1
(Address Pointer)
Aux. Reg.
2
Bank of
Primary Reg.
Subport Fh
Subport Eh
Module M2
Aux. Reg.
6
Module M3
Primary Reg.
Subport 1
Subport 0
3
1
Primary Reg.
4
5
I/O bus
Primary Reg.
7
to other modules
Example of
qFORTH
Program
Code
Indirect Subport Access
(Subport Register Write)
1
Addr. (M1) Addr. (ASW) OUT
2
Addr. (SPort) Addr. (M1) OUT
3
SPort_Data Addr. (M1) OUT
(Subport Register Read)
1
Addr. (M1) Addr. (ASW) OUT
2
Addr. (SPort) Addr. (M1) OUT
3
Addr. (M1) IN
(Subport Register Write Byte)
1
Addr. (M1) Addr. (ASW) OUT
2
Addr. (SPort) Addr. (M1) OUT
3
SPort_Data (lo) Addr. (M1) OUT
3
SPort_Data (hi) Addr. (M1) OUT
(Subport Register Read Byte)
1
Addr. (M1) Addr. (ASW) OUT
2
Addr. (SPort) Addr. (M1) OUT
3
Addr. (M1) IN
3
Addr. (M1) IN
(Auxiliary Register Read)
1
Addr. (M1) Addr. (ASW) OUT
2
Addr. (M1) IN
Dual Register Access
(Primary Register Write)
4 Pirm._Data Addr. (M2) OUT
Single Register Access
(Primary Register Write)
7 Prim._Data Address (M3) OUT
(Auxiliary Register Write)
5 Addr. (M2) Addr. (ASW) OUT
6 Aux._Data Addr. (ASW) OUT
(Primary Register Read)
4
Addr. (M2) IN
(Primary Register Read)
7
Address (M3) IN
(Auxiliary Register Read)
5 Addr. (M2) Addr. (ASW) OUT
6
Addr. (M2) IN
(Auxiliary Register Write Byte)
5 Addr. (M2) Addr. (ASW) OUT
6 _{Aux._Data (lo) Addr. (M2) OUT}
6 _{Aux._Data (hi) Addr. (M2) OUT}
Addr. (ASW) = Auxiliary Switch Module Address
Addr. (Mx) = Module Mx Address
Addr. (SPort) = Subport Address
Prim._Data = data to be written into Primary Register
Aux._Data = data to be written into Auxiliary Register
Aux._Data (lo) = data to be written into Auxiliary Register (low nibble)
Aux._Data (hi) = data to be written into Auxiliary Register (high nibble)
SPort_Data (lo) = data to be written into Subport (low nibble)
SPort_Data (hi) = data to be written into Subport (high nibble)
22 ATAM510
4711B–4BMCU–01/05