ATMEGA6450_14 Datasheet, PDF (219/362 Pages) ATMEL Corporation – High Endurance Non-volatile Memory Segments

ATmega325/3250/645/6450
• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not
provided.
When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the
TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP
pins are internally pulled high and the JTAG is enabled for Boundary-scan and programming.
The device is shipped with this fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni-
tored by the debugger to be able to detect external reset sources. The debugger can also pull
the RESET pin low to reset the whole system, assuming only open collectors on the reset line
are used in the application.
Figure 24-1. Block Diagram
I/O PORT 0
DEVICE BOUNDARY
BOUNDARY SCAN CHAIN
TDI
TDO
TCK
TMS
TAP
CONTROLLER
INSTRUCTION
REGISTER
ID
REGISTER
M
U
BYPASS
X
REGISTER
BREAKPOINT
SCAN CHAIN
ADDRESS
DECODER
JTAG PROGRAMMING
INTERFACE
FLASH Address
MEMORY
Data
BREAKPOINT
UNIT
OCD STATUS
AND CONTROL
INTERNAL
SCAN
CHAIN
AVR CPU
PC
Instruction
FLOW CONTROL
UNIT
DIGITAL
PERIPHERAL
UNITS
JTAG / AVR CORE
COMMUNICATION
INTERFACE
ANALOG
PERIPHERIAL
UNITS
Analog inputs
Control & Clock lines
I/O PORT n
2570N–AVR–05/11
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