ATMEGA6450_14 Datasheet, PDF (205/362 Pages) ATMEL Corporation – High Endurance Non-volatile Memory Segments

2570N–AVR–05/11
ATmega325/3250/645/6450
with Auto triggering from a source other than the ADC Conversion Complete, each conversion
will require 25 ADC clocks. This is because the ADC must be disabled and re-enabled after
every conversion.
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times, see Table 23-1.
Figure 23-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
First Conversion
Next
Conversion
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
1
2
12 13 14 15 16 17 18 19 20 21 22 23 24 25
1
2
3
MUX and REFS
Update
Sample & Hold
Conversion
Complete
Sign and MSB of Result
LSB of Result
MUX and REFS
Update
Figure 23-5. ADC Timing Diagram, Single Conversion
One Conversion
Next Conversion
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
1
2
3
4
5
6
7
8
9
10 11 12 13
123
Sample & Hold
MUX and REFS
Update
Conversion
Complete
Sign and MSB of Result
LSB of Result
MUX and REFS
Update
Figure 23-6. ADC Timing Diagram, Auto Triggered Conversion
One Conversion
Next Conversion
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
1
2
3
4
5
6
7
8
9
10 11 12 13
1
2
MUX and REFS
Update
Sample &
Hold
Conversion
Complete
Sign and MSB of Result
LSB of Result
Prescaler
Reset
205