ATTINY88_14 Datasheet, PDF (202/302 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 8K Bytes In-System

21.3.1
Pin Mapping
The pin mapping is listed in Table 21-7.
Table 21-7. Pin Mapping Serial Programming
Symbol
Pins
I/O
MOSI
PB3
I
MISO
PB4
O
SCK
PB5
I
Description
Serial Data in
Serial Data out
Serial Clock
21.3.2
Programming Algorithm
When writing serial data to the ATtiny48/88, data is clocked on the rising edge of SCK. When
reading data from the ATtiny48/88, data is clocked on the falling edge of SCK. See Figure 22-9
on page 217 and Figure 22-10 on page 217 for timing details.
To program and verify the ATtiny48/88 in the serial programming mode, the following sequence
is recommended (See Serial Programming Instruction set in Table 21-8 on page 203):
1. Power-up sequence: apply power between V_CC and GND while RESET and SCK are
set to “0”.
– In some systems, the programmer can not guarantee that SCK is held low during
power-up. In this case, RESET must be given a positive pulse after SCK has been
set to '0'. The duration of the pulse must be at least t_RST plus two CPU clock cycles.
See Table 22-3 on page 209 for definition of minimum pulse width on RESET pin,
t_RST
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of syn-
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction.
– Whether the echo is correct or not, all four bytes of the instruction must be
transmitted.
– If the 0x53 did not echo back, give RESET a positive pulse and issue a new
Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
a time by supplying the 6 LSB of the address and data together with the Load Program
Memory Page instruction.
– To ensure correct loading of the page, the data low byte must be loaded before data
high byte is applied for a given address.
– The Program Memory Page is stored by loading the Write Program Memory Page
instruction with the 7 MSB of the address.
– If polling (RDY/BSY) is not used, the user must wait at least t_{WD_FLASH} before issuing
the next page (See Table 21-9). Accessing the serial programming interface before
the Flash write operation completes can result in incorrect programming.
5. The EEPROM can be programmed one byte or one page at a time.
– A: The EEPROM array is programmed one byte at a time by supplying the address
and data together with the appropriate Write instruction. An EEPROM memory
location is first automatically erased before new data is written. If polling (RDY/BSY)
is not used, the user must wait at least t_{WD_EEPROM} before issuing the next byte (See
202 ATtiny48/88
8008H–AVR–04/11