ATTINY88_14 Datasheet, PDF (118/302 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 8K Bytes In-System

Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f_ExtClk < f_{clk_I/O}/2) given a 50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by oscillator source tolerances, it is recommended that maximum fre-
quency of an external clock source is less than f_{clk_I/O}/2.5.
An external clock source can not be prescaled.
Figure 13-2. Prescaler for Timer/Counter0 and Timer/Counter1⁽¹⁾
clk_I/O
Clear
PSRSYNC
T0
Synchronization
T1
Synchronization
clk_T1
clk_T0
Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 13-1.
13.4 Register Description
13.4.1
GTCCR – General Timer/Counter Control Register
Bit
7
6
5
4
3
2
0x23 (0x43)
TSM
–
–
–
–
–
Read/Write
R/W
R
R
R
R
R
Initial Value
0
0
0
0
0
0
1
0
–
PSRSYNC GTCCR
R
R/W
0
0
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRSYNC bit is kept, hence keeping the corresponding prescaler
reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can
be configured to the same value without the risk of one of them advancing during configuration.
118 ATtiny48/88
8008H–AVR–04/11