AT91M55800A_14 Datasheet, PDF (200/256 Pages) ATMEL Corporation – High-performance 32-bit RISC Architecture

20.7.2 SPI Mode Register
Register Name: SP_MR
Access Type:
Read/Write
Reset State:
0
Offset:
0x04
31
30
29
23
22
21
–
–
–
15
14
13
–
–
–
7
6
5
LLB
–
–
28
27
DLYBCS
20
19
–
12
11
–
–
4
3
–
MCK32
26
25
18
17
PCS
10
9
–
–
2
1
PCSDEC
PS
• MSTR: Master/Slave Mode (Code Label SP_MSTR)
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
MSTR configures the SPI Interface for either master or slave mode operation.
• PS: Peripheral Select
24
16
8
–
0
MSTR
PS
Selected PS
0
Fixed Peripheral Select
1
Variable Peripheral Select
Code Label: SP_PS
SP_PS_FIXED
SP_PS_VARIABLE
• PCSDEC: Chip Select Decode (Code Label SP_PCSDEC)
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 16 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder.
The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules:
SP_CSR0defines peripheral chip select signals 0 to 3.
SP_CSR1defines peripheral chip select signals 4 to 7.
SP_CSR2defines peripheral chip select signals 8 to 11.
SP_CSR3defines peripheral chip select signals 12 to 15⁽¹⁾.
Note: 1. The 16th state corresponds to a state in which all chip selects are inactive. This allows a different clock configuration to be
defined by each chip select register.
• MCK32: Clock Selection (Code Label SP_DIV32)
0 = SPI Master Clock equals MCK.
1 = SPI Master Clock equals MCK/32.
200 AT91M5880A
1745F–ATARM–06-Sep-07