AT40K05AL_14 Datasheet, PDF (2/51 Pages) ATMEL Corporation – 5K – 50K Gates Coprocessor FPGA with FreeRAM

Table 1. AT40KAL Family⁽¹⁾
Device
Usable Gates
Rows x Columns
Cells
Registers
RAM Bits
I/O (Maximum)
AT40K05AL
5K – 10K
16 x 16
256
496⁽¹⁾
2,048
128
AT40K10AL
10K – 20K
24 x 24
576
954⁽¹⁾
4,608
192
Note: 1. Packages with FCK will have eight less registers.
AT40K20AL
20K – 30K
32 x 32
1,024
1,520⁽¹⁾
8,192
256
AT40K40AL
40K – 50K
48 x 48
2,304
3,048⁽¹⁾
18,432
384
1. Description
The AT40KAL is a family of fully PCI-compliant, SRAM-based FPGAs with distributed 10ns programmable
synchronous/asynchronous, dual-port/single-port SRAM, eight global clocks, Cache Logic ability (partially or fully
reconfigurable without loss of data), automatic component generators, and range in size from 5,000 to 50,000
usable gates. I/O counts range from 114 to 161 in industry standard packages ranging from 144-pin LQFP to
208-pin PQFP, and support 3.3V designs.
The AT40KAL is designed to quickly implement high-performance, large gate count designs through the use of
synthesis and schematic-based tools used on a PC or Sun platform. The Atmel design tools provide seamless
integration with industry standard tools such as Synplicity, ModelSim, Exemplar, and Viewlogic.
The AT40KAL can be used as a coprocessor for high-speed (DSP/processor-based) designs by implementing a
variety of computation intensive, arithmetic functions. These include adaptive finite impulse response (FIR) filters,
fast Fourier transforms (FFT), convolvers, interpolators and discrete-cosine transforms (DCT) that are required for
video compression and decompression, encryption, convolution, and other multimedia applications.
1.1 Fast, Flexible, and Efficient SRAM
The AT40KAL FPGA offers a patented distributed 10ns SRAM capability where the RAM can be used without
losing logic resources. Multiple independent, synchronous or asynchronous, and dual-port or single-port RAM
functions (FIFO, scratch pad, etc.) can be created using Atmel’s macro generator tool.
1.2 Fast, Efficient Array, and Vector Multipliers
The AT40KAL’s patented 8-sided core cell with direct horizontal, vertical and diagonal cell-to-cell connections
implements ultra fast array multipliers without using any busing resources. The AT40KAL Cache Logic capability
enables a large number of design coefficients and variables to be implemented in a very small amount of silicon,
enabling vast improvement in system speed at much lower cost than conventional FPGAs.
2
AT40KAL Series FPGA [Datasheet]
Atmel-2818G-FPGA-AT40KAL-Series-Datasheet_092013