AT40K05AL_14 Datasheet, PDF (14/51 Pages) ATMEL Corporation – 5K – 50K Gates Coprocessor FPGA with FreeRAM

7. Clocking Scheme
There are eight Global Clock buses (GCK1 – GCK8) on the AT40KAL FPGA. Each of the eight dedicated Global
Clock buses is connected to one of the dual-use Global Clock pins. Any clocks used in the design should use
global clocks where possible: this can be done by using Assign Pin Locks to lock the clocks to the Global Clock
locations. In addition to the eight Global Clocks, there are four Fast Clocks (FCK1 – FCK4), two per edge column of
the array for PCI specification. For AT40KAL FPGAs, even the derived clocks can be routed through the Global
network. Access points are provided in the corners of the array to route the derived clocks into the global clock
network. The IDS software tools handle derived clocks to global clock connections automatically if used.
Each column of an array has a “Column Clock mux” and a “Sector Clock mux”. The Column Clock mux is at the top
of every column of an array and the Sector Clock mux is at every four cells. The Column Clock mux is selected
from one of the eight Global Clock buses. The clock provided to each sector column of four cells is inverted,
non-inverted or tied off to zero, using the Sector Clock mux to minimize the power consumption in a sector that has
no clocks. The clock can either come from the Column Clock or from the Plane 4 express bus, see Figure 7-1. The
extreme-left Column Clock mux has two additional inputs, FCK1 and FCK2, to provide fast clocking to left-side
I/Os. The extreme-right Column Clock mux has two additional inputs as well, FCK3 and FCK4, to provide fast
clocking to right-side I/Os.
The register in each cell is triggered on a rising clock edge by default. Before configuration on power-up, constant
zero is provided to each register’s clock pins. After configuration on power-up, the registers either set or reset,
depending on the user’s choice.
The clocking scheme is designed to allow efficient use of multiple clocks with low clock skew, both within a column
and across the core cell array.
14 AT40KAL Series FPGA [Datasheet]
Atmel-2818G-FPGA-AT40KAL-Series-Datasheet_092013