ATMEGA169V_14 Datasheet, PDF (199/365 Pages) ATMEL Corporation – Non-volatile Program and Data Memories

ATmega169/V
Changing Channel or
Reference Selection
ADC Input Channels
ADC Voltage Reference
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a tem-
porary register to which the CPU has random access. This ensures that the channels
and reference selection only takes place at a safe point during the conversion. The
channel and reference selection is continuously updated until a conversion is started.
Once the conversion starts, the channel and reference selection is locked to ensure a
sufficient sampling time for the ADC. Continuous updating resumes in the last ADC
clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the
conversion starts on the following rising ADC clock edge after ADSC is written. The user
is thus advised not to write new channel or reference selection values to ADMUX until
one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic.
Special care must be taken when updating the ADMUX Register, in order to control
which conversion will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If
the ADMUX Register is changed in this period, the user cannot tell if the next conversion
is based on the old or the new settings. ADMUX can be safely updated in the following
ways:
1. When ADATE or ADEN is cleared.
2. During conversion, minimum one ADC clock cycle after the trigger event.
3. After a conversion, before the Interrupt Flag used as trigger source is
cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next
ADC conversion.
When changing channel selections, the user should observe the following guidelines to
ensure that the correct channel is selected:
In Single Conversion mode, always select the channel before starting the conversion.
The channel selection may be changed one ADC clock cycle after writing one to ADSC.
However, the simplest method is to wait for the conversion to complete before changing
the channel selection.
In Free Running mode, always select the channel before starting the first conversion.
The channel selection may be changed one ADC clock cycle after writing one to ADSC.
However, the simplest method is to wait for the first conversion to complete, and then
change the channel selection. Since the next conversion has already started automati-
cally, the next result will reflect the previous channel selection. Subsequent conversions
will reflect the new channel selection.
The reference voltage for the ADC (V_REF) indicates the conversion range for the ADC.
Single ended channels that exceed V_REF will result in codes close to 0x3FF. V_REF can be
selected as either AVCC, internal 1.1V reference, or external AREF pin.
AVCC is connected to the ADC through a passive switch. The internal 1.1V reference is
generated from the internal bandgap reference (V_BG) through an internal buffer. In either
case, the external AREF pin is directly connected to the ADC, and the reference voltage
can be made more immune to noise by connecting a capacitor between the AREF pin
and ground. V_REF can also be measured at the AREF pin with a high impedant voltme-
ter. Note that V_REF is a high impedant source, and only a capacitive load should be
connected in a system.
If the user has a fixed voltage source connected to the AREF pin, the user may not use
the other reference voltage options in the application, as they will be shorted to the
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