ATMEGA169_14 Datasheet, PDF (197/365 Pages) ATMEL Corporation – Non-volatile Program and Data Memories

2514P–AVR–07/06
ATmega169/V
In Free Running mode, a new conversion will be started immediately after the conver-
sion completes, while ADSC remains high. For a summary of conversion times, see
Table 87.
Figure 86. ADC Timing Diagram, First Conversion (Single Conversion Mode)
First Conversion
Next
Conversion
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
1
2
12 13 14 15 16 17 18 19 20 21 22 23 24 25
1
2
3
MUX and REFS
Update
Sample & Hold
Conversion
Complete
Sign and MSB of Result
LSB of Result
MUX and REFS
Update
Figure 87. ADC Timing Diagram, Single Conversion
One Conversion
Next Conversion
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
1
2
3
4
5
6
7
8
9
10 11 12 13
1
2
3
Sample & Hold
MUX and REFS
Update
Conversion
Complete
Sign and MSB of Result
LSB of Result
MUX and REFS
Update
Figure 88. ADC Timing Diagram, Auto Triggered Conversion
One Conversion
Next Conversion
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
1
2
3
4
5
6
7
8
9
10 11 12 13
12
MUX and REFS
Update
Sample &
Hold
Conversion
Complete
Sign and MSB of Result
LSB of Result
Prescaler
Reset
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