ATMEGA6490V_14 Datasheet, PDF (194/392 Pages) ATMEL Corporation – High Endurance Non-volatile Memory Segments

• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCK).
Table 19-12. UCPOLn Bit Settings
UCPOLn
Transmitted Data Changed
(Output of TxD Pin)
0
Rising XCK Edge
1
Falling XCK Edge
Received Data Sampled
(Input on RxD Pin)
Falling XCK Edge
Rising XCK Edge
19.11.5
UBRRnL and UBRRnH – USART Baud Rate Registers n
Bit
15
14
13
12
11
–
–
–
–
UBRRn[7:0]
7
6
5
4
3
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
0
0
10
9
UBRRn[11:8]
2
1
R/W
R/W
R/W
R/W
0
0
0
0
8
UBRRnH
UBRRnL
0
R/W
R/W
0
0
• Bit 15:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRnH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRnH contains the four
most significant bits, and the UBRRnL contains the eight least significant bits of the USART
baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud
rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler.
194 ATmega329/3290/649/6490
2552K–AVR–04/11