ATTINY1634_14 Datasheet, PDF (19/259 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 16KB In-system

When powered by heavily filtered supplies, the supply voltage, V_CC, is likely to rise or fall slowly on power-up and power-
down. Slow rise and fall times may put the device in a state where it is running at supply voltages lower than specified. To
avoid problems in such situations, see Section 6.3.5 “Preventing EEPROM Corruption” on page 20.
The EEPROM has a minimum endurance of 100,000 write/erase cycles.
6.3.1
Programming Methods
There are two methods for EEPROM programming:
● Atomic byte programming – this is the simple mode of programming where target locations are erased and written in
a single operation. In this operating mode the target is guaranteed to always be erased before writing but
programming times are longer.
● Split byte programming – it is possible to split the erase and write cycle into two different operations. This is useful
when short access times are required, for example, when supply voltage is falling. In order to take advantage of this
method, target locations must be erased before writing to them. This can be done at times when the system allows
time-critical operations, typically at start-up and initialization.
The programming method is selected using the EEPROM programming mode bits (EEPM1 and EEPM0) in the EEPROM
control register (EECR) (see Table 6-4 on page 23). The write and erase times are given in the same table.
Because EEPROM programming takes some time, the application must wait for one operation to complete before starting
the next. This can be done by either polling the EEPROM program enable bit (EEPE) in the EEPROM control register
(EECR), or via the EEPROM ready interrupt. The EEPROM interrupt is controlled by the EEPROM ready interrupt enable
(EERIE) bit in EECR.
6.3.2
Read
To read an EEPROM memory location, follow the procedure below:
1. Poll the EEPROM program enable bit (EEPE) in the EEPROM control register (EECR) to make sure no other
EEPROM operations are in process. If set, wait to clear.
2. Write the target address to the EEPROM address registers (EEARH/EEARL).
3. Start the read operation by setting the EEPROM read enable bit (EERE) in the EEPROM control register (EECR).
During the read operation, the CPU is stopped for four clock cycles before executing the next instruction.
4. Read data from the EEPROM data register (EEDR).
6.3.3
Erase
In order to prevent unintentional EEPROM writes, a specific procedure must be followed to erase memory locations. To
erase an EEPROM memory location, follow the procedure below:
1. Poll the EEPROM program enable bit (EEPE) in the EEPROM control register (EECR) to make sure no other
EEPROM operations are in process. If set, wait to clear.
2. Set mode of programming to erase by writing the EEPROM programming mode bits (EEPM0 and EEPM1) in the
EEPROM control register (EECR).
3. Write the target address to the EEPROM address registers (EEARH/EEARL).
4. Enable erase by setting the EEPROM master program enable (EEMPE) in the EEPROM control register (EECR).
Within four clock cycles, start the erase operation by setting the EEPROM program enable bit (EEPE) in the
EEPROM control register (EECR). During the erase operation, the CPU is stopped for two clock cycles before
executing the next instruction.
The EEPE bit remains set until the erase operation has completed. While the device is busy programming, it is not possible
to perform any other EEPROM operations.
ATtiny1634 [PRELIMINARY DATASHEET]
19
9296C–AVR–07/14