ATTINY1634_14 Datasheet, PDF (123/259 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 16KB In-system

Writing the TWCMD bits automatically releases the SCL line and clears the TWCH and slave interrupt flags.
TWAA and TWCMDn bits can be written at the same time. Acknowledge action is then executed before the command is
triggered.
The TWCMDn bits are strobed and always read as “0”.
15.5.3 TWSSRA – TWI Slave Status register A
Bit
(0x7D)
Read/Write
Initial Value
7
TWDIF
R/W
0
6
TWASIF
R/W
0
5
TWCH
R
0
4
TWRA
R
0
3
TWC
R/W
0
2
TWBE
R/W
0
1
TWDIR
R
0
0
TWAS
R
0
TWSSRA
● Bit 7 – TWDIF: TWI Data Interrupt Flag
This flag is set when a data byte has been successfully received, i.e., no bus errors or collisions have occurred during the
operation. When this flag is set, the slave forces the SCL line low, stretching the TWI clock period. The SCL line is released
by clearing the interrupt flags.
Writing a “1” to this bit clears the flag. This flag is also automatically cleared when writing a valid command to the TWCMDn
bits in TWSCRB.
● Bit 6 – TWASIF: TWI Address/Stop Interrupt Flag
This flag is set when the slave detects that a valid address has been received or when a transmit collision has been
detected. When this flag is set, the slave forces the SCL line low, stretching the TWI clock period. The SCL line is released
by clearing the interrupt flags.
If TWASIE in TWSCRA is set, a STOP condition on the bus also sets TWASIF. A STOP condition sets the flag only if the
system clock is faster than the minimum bus free time between STOP and START.
Writing a “1” to this bit clears the flag. This flag is also automatically cleared when writing a valid command to the TWCMDn
bits in TWSCRB.
● Bit 5 – TWCH: TWI Clock Hold
This bit is set when the slave is holding the SCL line low.
This bit is read-only and set when TWDIF or TWASIF is set. The bit can be cleared indirectly by clearing the interrupt flags
and releasing the SCL line.
● Bit 4 – TWRA: TWI Receive Acknowledge
This bit contains the most recently received acknowledge bit from the master.
This bit is read-only. When “0”, the most recent acknowledge bit from the master was ACK and, when “1”, the most recent
acknowledge bit was NACK.
● Bit 3 – TWC: TWI Collision
This bit is set when the slave is unable to transfer a high data bit or a NACK bit. When a collision is detected, the slave
commences normal operation and disables data and acknowledges output. No low values are shifted out onto the SDA line.
This bit is cleared by writing a “1” to it. The bit is also cleared automatically when a START or repeated START condition is
detected.
● Bit 2 – TWBE: TWI Bus Error
This bit is set when an illegal bus condition has occurred during a transfer. An illegal bus condition occurs if a repeated
START or STOP condition is detected and the number of bits from the previous START condition is not a multiple of nine.
This bit is cleared by writing a “1” to it.
● Bit 1 – TWDIR: TWI Read/Write Direction
This bit indicates the direction bit from the last address packet received from a master. When this bit is “1”, a master read
operation is in progress. When the bit is “0”, a master write operation is in progress.
ATtiny1634 [PRELIMINARY DATASHEET] 123
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