AT572D940HF Datasheet, PDF (19/39 Pages) ATMEL Corporation – DIOPSIS 940HF ARM926EJ-S PLUS ONE GFLOPS DSP

AT572D940HF Preliminary
5.3.11
mAgicV AHB master interface
mAgicV VLIW DSP is equipped with an AHB master which supports mAgicV DMA engine.
5.3.12
AHB DMA on Data Memory System
At every cycle, one port of the on-chip Data Memory System is reserved to fetch/store the activ-
ity driven by the DMA Engine. The DMA to the external memories or to the other devices
mapped on the AHB System Bus is supported by mAgicV AHB master interface. The DMA
engine can generate stride access to the external memory. The DMA transfers to and from the
on-chip Memory can be executed in parallel with the full speed core instructions execution with
zero-overhead and without the intervention of the core processor, except for initiating it.
5.3.13
AHB DMA on Program Memory
The on-chip Program Memory of mAgicV is a dual port. One port is reserved to the instruction
fetch and the other to the DMA engine. In parallel with the activities of the core, a DMA can be
activated between the external memories and the other devices mapped on the AHB System
Bus.
5.3.14
mAgicV AHB slave interface
External AHB masters, like ARM and JTAG can access the memories and the registers of mAg-
icV DSP through mAgicV AHB slave interface. In Debug mode (see Section 5.3.15.3 below) all
the internal resources are memory mapped, while in run mode or sleep mode access restrictions
apply (see Section 5.3.15.1 and Section 5.3.15.2 below). At every cycle, one port of the Data
Memory System is reserved to read/store accesses performed through the AHB slave interface.
Example of usage: data sampled by AD Converters can be written inside the mAgicV Data Mem-
ory in parallel to the DMA (through the master port) and the VLIW operations.
5.3.15
Operating Modes of mAgicV
mAgicV VLIW DSP can operate in three operating modes: Run mode, Sleep mode and Debug
mode. The access allowed to the different resources through the AHB slave port depends on the
status mode:
5.3.15.1
Run Mode
In Run Mode, a mAgicV VLIW program is under execution. mAgicV can access external
resources through its AHB master interface. Control and status registers are visible. One port of
the Data Memory System is accessible through the AHB Slave port.
5.3.15.2
Sleep Mode
In Sleep Mode, the AHB Master and Slave port and the DMA engine are still active. However,
only “non-destructive access paths” are guaranteed through the AHB slave interface. Control
and Status registers are active. Data and Address Registers are frozen (readable but not
writable).
5.3.15.3
Debug Mode
In Debug Mode, mAgicV suspends its execution (if any) and debug paths are allowed. Data and
Program memories are readable. Data and Address registers are readable. Pipeline registers
are frozen. Any external master, like JTAG or the ARM can access the internal resources of
mAgicV DSP for debug purpose. The ability of the ARM to access internal mAgicV resources in
Debug Mode can be used for initialization and also for debugging purposes. By accessing the
Command Register, the ARM can change the operating status of the DSP (Run/System Mode),
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