AT572D940HF Datasheet, PDF (1/39 Pages) ATMEL Corporation – DIOPSIS 940HF ARM926EJ-S PLUS ONE GFLOPS DSP

Features
• DIOPSIS^® Dual Core System Integrating an ARM926EJ-S^™ ARM^® Thumb^® Processor
Core and a mAgicV VLIW DSP of the Magic DSP^™ family, optimized for Audio,
Communication and Beam-forming Applications
• High Performance MagicV VLIW DSP
– 1 GFLOPS - 1.6 Gops at 100 MHz
– AHB Master Port, integrated DMA Engine and AHB Slave Port
– Up to 10 Arithmetic Operations per Cycle (4 Multiply, 2 Add/subtract, 1 Add, 1
Subtract 40-bit Floating Point and 32-bit Integer) Allowing Single Cycle FFT
Butterfly
– Native Support for Complex Arithmetic and Vectorial SIMD Operations: One
Complex Multiply with Dual Add/sub per Clock Cycle or Two Real Multiply and Two
Add/sub or Simple Scalar Operations
– 32-bit Integer and IEEE^® 40-bit Extended Precision Floating Point Numeric Format
– 16-port Data Register File: 256 Registers Organized in Two 128-register Banks
– 5-issue predicated VLIW Architecture with Orthogonal ISA, Code Compression
and Hardware Support for Code Efficient Software Pipeline Loops
– 6 Accesses per Cycle Data Memory System (4 Accesses per Cycle for VLIW
Operations + 2 Accesses per Cycle for DMA Transfers) supported by Flexible
Addressing Capability
– 2 Independent Address Generation Units Operating on a 64 Registers Address
Register File Supporting Complex or Micro-Vectorial Accesses, and DSP features:
Programmable Stride and Circular Buffers
– 1.7 Mbits of On-chip SRAM:
– 16 K x 40-bit Data Memory Locations (6 Memory Accesses per Cycle)
– 8 K x 128-bit Dual Port Program Memory Location, Equivalent to ~50K DSP
Assembler Instructions (typical) thanks to Code Compression and SW Pipelining
– DMA Access to the External Program and Data Memory
– Three Main Operating Modes: Run, Debug and Sleep Modes
– User Mode and Privileged Interrupt Service Mode
– Efficient Optimizing Assembler and C-Oriented Architecture: Allows Easy
Exploitation of the Available Hardware Parallelism
• ARM926EJ-S ARM Thumb Processor
– DSP instruction extensions
– ARM Jazelle^® Technology for Java^® Acceleration
– 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
– 220MIPS at 200MHz
– Memory Management Unit
– EmbeddedICE^™ In-circuit Emulation, Debug Communication Channel Support
• Efficient ARM - DSP Interface through AHB master and slave ports, Memory Mapped
Registers and Ports, Interrupt Lines and Semaphores
• Additional Embedded Memories
– 32-KByte of internal ROM, two-cycle access at maximum bus speed
– 48-KByte of internal SRAM, single-cycle access at maximum processor or bus
speed
• External Bus Interface (EBI)
– Supports SDRAM, Static Memory, SmartMedia^® and NAND Flash, CompactFlash^®
• USB
– USB 2.0 Full Speed (12 Mbits per second) Host Double Port
DIOPSIS 940HF
ARM926EJ-S PLUS
ONE GFLOPS DSP
AT572D940HF
Preliminary
Summary
NOTE: This is a summary document.
The complete document is available
under NDA. For more information,
please contact your local Atmel sales
office.
7010AS–DSP–07/07