ATMEGA48PA_14 Datasheet, PDF (187/326 Pages) ATMEL Corporation – 131 Powerful Instructions – Most Single Clock Cycle Execution

22.5
Overview of the TWI Module
The TWI module is comprised of several submodules, as shown in Figure 22-9. All registers drawn in a thick line are
accessible through the AVR data bus.
Figure 22-9. Overview of the TWI Module
SCL
SDA
Slew-rate Spike
Control Filter
Slew-rate Spike
Control Filter
Bus Interface Unit
START/ STOP
Control
Spike Suppression
Arbitration detection
Address/ Data Shift
Register (TWDR)
Ack
Bit Rate Generator
Prescaler
Bit Rate Register
(TWBR)
Address Match Unit
Address Register
(TWAR)
Address Comparator
Control Unit
Status Register
(TWSR)
Control Register
(TWCR)
State Machine and
Status control
22.5.1 SCL and SDA Pins
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in order to
conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50ns. Note
that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins,
as explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need for external ones.
22.5.2 Bit Rate Generator Unit
This unit controls the period of SCL when operating in a master mode. The SCL period is controlled by settings in the TWI bit
rate register (TWBR) and the Prescaler bits in the TWI status register (TWSR). Slave operation does not depend on bit rate
or prescaler settings, but the CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency.
Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. The SCL frequency is
generated according to the following equation:
SCL frequency = _1---6-----+-----2---(C--T--P--W--U----B-C---R-l--o-)--c-_×--k---₍-f-P-r--e-r--eq--s-u--c-e-a--n-l--ce--yr--V-----a--l--u---e---₎-
ATmega48PA/88PA/168PA [DATASHEET] 187
9223F–AVR–04/14