ATA664251_14 Datasheet, PDF (179/290 Pages) ATMEL Corporation – 16K Flash Microcontroller with LIN Transceiver

5.15.5.3 USISR – USI Status Register
The Status Register contains Interrupt Flags, line Status Flags and the counter value.
Bit
Read/Write
Initial Value
7
USISIF
R/W
0
6
USIOIF
R/W
0
5
USIPF
R/W
0
4
USIDC
R
0
3
2
1
0
USICNT3 USICNT2 USICNT1 USICNT0
R/W
R/W
R/W
R/W
0
0
0
0
USISR
● Bit 7 – USISIF: Start Condition Interrupt Flag
When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is detected. When output dis-
able mode or Three-wire mode is selected and (USICSx = 11_b & USICLK = 0) or (USICS = 10_b & USICLK = 0), any
edge on the SCK pin sets the flag.
An interrupt will be generated when the flag is set while the USISIE bit in USICR and the Global Interrupt Enable Flag
are set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing this bit will release the start
detection hold of USCL in Two-wire mode.
A start condition interrupt will wakeup the processor from all sleep modes.
● Bit 6 – USIOIF: Counter Overflow Interrupt Flag
This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An interrupt will be gener-
ated when the flag is set while the USIOIE bit in USICR and the Global Interrupt Enable Flag are set. The flag will only
be cleared if a one is written to the USIOIF bit. Clearing this bit will release the counter overflow hold of SCL in Two-
wire mode.
A counter overflow interrupt will wakeup the processor from Idle sleep mode.
● Bit 5 – USIPF: Stop Condition Flag
When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected. The flag is cleared
by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is useful when implementing Two-wire
bus master arbitration.
● Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value. The flag is only valid
when Two-wire mode is used. This signal is useful when implementing Two-wire bus master arbitration.
● Bits 3:0 – USICNT3..0: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the CPU.
The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a
Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits. The clock source depends of the
setting of the USICS1..0 bits. For external clock operation a special feature is added that allows the clock to be gener-
ated by writing to the USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an
external clock source (USICS1 = 1).
Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input (USCK/SCL) are can still be
used by the counter.
5.15.5.4 USICR – USI Control Register
Bit
Read/Write
Initial Value
7
USISIE
R/W
0
6
USIOIE
R/W
0
5
USIWM1
R/W
0
4
USIWM0
R/W
0
3
USICS1
R/W
0
2
USICS0
R/W
0
1
USICLK
W
0
0
USITC
W
0
USICR
The Control Register includes interrupt enable control, wire mode setting, Clock Select setting, and clock strobe.
● Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the Start Condition detector interrupt. If there is a pending interrupt when the USISIE
and the Global Interrupt Enable Flag is set to one, this will immediately be executed. Refer to the USISIF bit descrip-
tion in Section 5.15.5.3 “USISR – USI Status Register” on page 179.
ATA664251 [DATASHEET] 179
9269E–AUTO–06/14